The present invention relates generally to multiple processor systems, and in particular to a multiple processor system architecture with non-shared memory with interprocessor communication capability that is provided by permitting any processor of the system to access the memory of any other processor of the system.
Although multiple processor systems have been known for some time, they have become cost-effective only recently due to recent advances in microprocessor design and fabrication. Multiple processor systems achieve cost effective efficiencies over large, single-processor computing systems by breaking up tasks into smaller portions for concurrent execution and service by the multiple processors. Multiple processor systems are ideally suited for such tasks as transaction processing and concurrent database servers, to name just a few. The redundancy of the multiple processors of such systems also provides a basis for fault tolerant designs and architectures.
However, regardless of what uses are made of such multiple processor designs, the individual processors of such systems usually do not operate in a vacuum; that is, there is often a need for the individual processors of the system to communicate with one another. For example, some multiple processor architectures limit access to peripheral devices to specific processors, requiring other processors of the system to access the peripheral devices through these specific processors. Thus, a peripheral device used for secondary data storage (e.g., a disk system) may be controlled by an application process resident on a processor directly connected to that peripheral device. Another processor of the system, wishing to access that secondary data storage to store or retrieve data may need to do so through the connected processor, if the requesting processor is not so connected (i.e., does not have direct access). Such systems use some form of interprocessor communication system to provide such (indirect) access to peripheral devices.
Further, a fault tolerant design utilized by one known multiple processor architecture requires each processor of the system to use interprocessor communication to periodically broadcast a message to all other processors, indicating the broadcasting processor's well being. The absence of such a broadcast from any processor within a set period of time will cause a back-up process/processor to assume the workload previously handled by the (now supposed failed) primary processor.
However, interprocessor communication is not free; if an interprocessor communication system is not properly designed it can impose an undesirable time penalty on both the sending and receiving processors. This, in turn, can impact system efficiency by requiring the processors involved in the communication to take time to perform tasks associated with the communication process that could otherwise be used for data processing functions. For example, some traditional multiple processor architectures implement an interprocessor communication protocol that require the sender processor to first notify the receiving or destination processor that a message is forthcoming in order to allow the destination processor to prepare to receive the communication. The normal activity of the destination processor is thereby interrupted so that it can perform the necessary tasks of preparation. Next, the processing activity of the sender processor is then interrupted to involve it in the sending process, perhaps following the transmission with a signal or interrupt to the receiving processor to identify completion of the communication. Similarly, the destination processor must again interrupt other activity--if it can--so that it can handle the received data as necessary, and perhaps reply to the sender processor that the data has or has not been received. The reply, of course, will also have a number of associated interrupts to the sender and receiver processor.
If, for some reason, (e.g., insufficient memory space, involvement in uninterruptable activity, etc.) the receiving processor is unable to accept the communication, the sender processor will need to re-send the communication.
Of course, as the amount of messaging between the individual processors of a multiple processor system increases, interrupting a processor's normal duties for involvement in one or more of the aspects of interprocessor communication will, concomitantly, decrease or diminish the normal work activities of the processor, and with it its efficiency.
Some multiple processor architectures improve system efficiency by providing a communication medium exclusively for interprocessor communication, one that is separate from that medium used for input/output transfers between processors and peripheral devices. This, however, often requires a processor to operate according to two separate protocols, and increases system cost by the additional elements required for the interprocessor communication system.
Accordingly, it should be evident that an interprocessor communication system for multiple processor architectures and designs should impose as little burden as possible on processor involvement in order to maintain the efficiency of processor activities at a high level.